Fast Response Circuits for Voltage Droop Compensation

Voltage droops are unpredicted drops in the supply voltage of computer chips, which often occur as a result of nearby bursts of high intensity circuit activity. This proposal is concerned with fast voltage droops, where voltage drops within a few clock cycles. This means that any dynamic response must take place within one or at most two clock cycles.

A promising direction for combining the advantages of a stable reference clock with a small response time are mixed-signal control loops, in which voltage measurements are digitized and control decisions are taken by digital logic. However, digitally measuring a dynamically changing voltage may cause metastability of the sampling circuit.

Conventional approaches employ synchronizers to make the probability of metastable upsets negligible, which costs 2-3 clock cycles of additional delay.Based on results of the ERC starting grant project ""A Theory of Reliable Hardware,'' we provide a simple, compact circuit that guarantees the desired behavior without incurring synchronizer delay.

This yields a practical method for adaptive response to fast droops, which bears the promise of increasing computational efficiency.

Conservative estimates suggest performance improvements of at least 5%, which would be of substantial economical interest.The main obstacle to commercialization is a gap between theory and practice: Without an existing implementation, it takes a long time to develop a product and the associated risks are high.

In this project, we will overcome this hurdle by developing, producing, and evaluating an Application-Specific Integrated Circuit (ASIC) demonstrator for our approach.

We complement this primary goal by tasks aiming at maximizing impact: publication of results in high-profile scientific venues, patent protection to facilitate commercialization, and outreach to potential industry partners for developing products.