Integration of processes and moDules for the 2 nm node meeting Power Performance Area and Cost requirements

In the ID2PPAC project the technology solutions for the 2nm node identified in the preceding project IT2 will be consolidated and integrated with the objective to demonstrate that Performance Power Area and Cost (PPAC) requirements for this generation of leading edge logic technology can be achieved.

To continue the Moores law trajectory to the 2nm node, while meeting PPAC requirements, the combination of further advancements in EUV lithography & masks, 3D device structures, materials and metrology is required.

The strength of the project pivots on the focused engagement of leading expert partners in these key interlocking areas and a shared pilot line.The ID2PPAC project, is expected to enable IC-fabs to do EUV-based, single-print, High Volume Manufacturing for the 2nm node by 2025.

This technology evolution is driven by the growing demand for compute power which increases more than exponentially with time and has made the world migrate from 1 billion interconnected devices in the PC era to 10 billion in the Mobile + cloud era to the future Intelligence era in which there will be over 100 billion intelligent connected devices.

To enable this growth, the semiconductor industry is continuously pursuing technology innovations to realize this progress as has been predicted by Moores Law and will continue to do so.The project will also help to expand Europe's technological capacity to act in this field, which is crucial for digitization, (edge) AI and for solving national, European and global societal challenges and will strengthen the consortium of leading European companies and institutes active in this sector.