Design and validation of Ultra-Reprogrammable sOCs

The DUROC project sets clear and measurable main objectives to reach a TRL 4 from TRL 2 as follows in 2-years:•Specifiy and design the next generation of ultra-programmable SoC (ULTRA7) taking benefit of leasson learnt from DAHLIA project (TRL 2)•Introduce the ARM 73 processor for very high performance processing specificly designed for advanced process node•Validate the SoC on a rad-hard demonstrator in 7nm FinFET technology from TSMC (TRL 4)•Validate reliability and radiation hardening performance of 7nm FinFET (TRL 4)•Propose a strategy and development plan up to flight model for the next ultra-reprogrammable SoC (ULTRA7)•Define the right approach for future SiP use in space applicationsAt the end of the project, Europe will have all required technical information to be in a position to develop multiple components (SoC FPGA, ASIC etc) on 7nm FinFET which will be the most advanced process node for space.

DUROC will bring Europe to an unprecedent leadership position in VLSI electronic for space. DUROC will be the first critial step to develop the next generation of ultra-reprogrammable SoC after NG-ULTRA.

The ULTRA 7 will target the following objectives:•MPSoC ARM A73 64-bit processor scalability combining ARM R52 real-time control •More than 35 000 DMIPS (Millions Instructions per Second)•Radiation hardening reliability meeting space payload and platform applications requirements