Identifying and Optimising Worst-Case Latency Bounds in On-Chip Network Interconnects

On-chip interconnects have played a key role in the performance and scalability of multi-core and many-core processors over the past two decades. As those processors are deployed more and more often in time-sensitive and safety-critical applications such as automotive, aerospace and medical systems, it is becoming more important to ensure that their performance is good enough to satisfy all requirements even in worst-case scenarios.

This project will build on recent developments in response-time analysis and network calculus, which are the main real-time analysis methods to identify worst-case latency in on-chip networks. Research work will include a systematic comparison of both methods regarding tightness, complexity/performance and resilience to corner case scenarios, with specific focus on recently discovered effects such as downstream indirect interference and multi-point blocking, which have shown that many state-of-the-art methods are unsafe.

The expected outcome will be a methodology for the joint application of both analysis methods, aiming to support the exploration of design alternatives that are predictable (bounded worst-case latency) and efficient (worst-case closer to the average case), and to pave the way towards the inclusion of such analyses into commercial timing analysis tools.