Low-Power Programmable Switch Architecture

Now, how to reduce the power consumption of digital integrate circuit through low-power design has become one of the most important problems in the post-Moore era. This problem is particularly important in the field of programmable switch. Due to the enormous number of switches deployed, a slight increase in the power consumption of a single switch will lead to a significant increase in the total power consumption of the whole network and vice versa.

Therefore, the effect of reducing total power consumption through low-power design is substantial, and the contribution to reducing carbon emissions is self-evident.

Protocol Independent Switching Architecture (PISA) is the mainstream programmable switch architecture used in the research community. It has superiority in matching fields and packet processing operations, as well as higher flexibility of Software Defined Network operations. However, PISA architecture has inherent defects in power consumption performance due to its working principle and cannot enable low power design technologies directly.

In addition, most architecture-based research focuses on improving performance or function. Few research has made significant advances in power consumption performance and compatibility with low-power design technologies. Therefore, to enable low-power design technologies and reduce power consumption, the proposal of a new programmable switch architecture can be regarded as a feasible and promising solution.

This research focuses on designing a novel programmable switch architecture that can reduce the power consumption of programmable switches while maintaining similar or better performance compared to the current mainstream architecture PISA. Specifically, it can be divided into three parts: 1. Design a new programmable switch architecture that can enable low-power design technologies

and avoid the drawbacks of PISA in terms of power consumption. 2. Investigate the advanced low power design technology Dynamic Frequency and Voltage Scaling (DVFS) on new architecture. 3. Develop the compiler and development tools for new architecture

In the PISA architecture, the pipeline used to process packages is divided into multiple stages only at the software level. However, this can lead to waste of hardware resources and power consumption. Therefore, we can separate these stages at the hardware level by designing a new architecture, and only use the required stages when forming the pipeline.

This design also allows the new architecture to use low-power design technologies to reduce the power consumption. For example, using clock gating and power gating to completely shut down the unused stages.

DVFS is one of the most powerful low-power design technologies. It can change the operating frequency and voltage of the switch with changes in traffic to achieve the minimum power consumption. However, changes in traffic cannot be predicted.

If DVFS only uses traffic as an indicator, frequent changes in frequency and voltage of the switch will result in more waste of power consumption. Therefore, there is currently no research focuses on the application of DVFS in programmable switches. This research will implement DVFS in programmable switches by improving the new architecture.

And predict traffic by monitoring traffic at the macro level through control planes, as well as constraining traffic switching strategies, to reduce power consumption and increase power efficiency of the switch.

Besides, to facilitate the use of new architecture for future research and community, it is necessary to design a compiler and corresponding development tools (Software package, software framework, visual programming) for new architecture. All these tools will be open source, which can reduce the learning cost for the development of new architecture and make the new architecture more widely used.

This project falls within the EPSRC ICT networks and distributed systems research area.