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| Funder | Engineering and Physical Sciences Research Council |
|---|---|
| Recipient Organization | University of Edinburgh |
| Country | United Kingdom |
| Start Date | Aug 31, 2021 |
| End Date | Aug 30, 2023 |
| Duration | 729 days |
| Number of Grantees | 2 |
| Roles | Student; Supervisor |
| Data Source | UKRI Gateway to Research |
| Grant ID | 2590776 |
Continuing the line of thought from previous work from my supervisors and senior research group member, the overarching goal of this research is to synthesize processor hardware, specifically hardware to interface between a processor and complex memory system. This consists of several sub-goals. These sub-goals are to determine the formal/mathematical specification
of the processor, it's details, and the processor's system details that are required in order to have a software tool correctly synthesize hardware units for processors. These sub-goals will also require the development of analysis procedures, likely involving a combination of formal and heuristic analyses for synthesizing correct and functional hardware, and
potentially optimizing the performance of the generated hardware. Additionally, the tool would need an appropriate internal representation of the processor's hardware structures in order to perform analyses. The broader question this would work towards answering is if it is possible or reasonable to synthesize hardware for a complex system
such as a processor. This would develop novel engineering methodologies and answer multiple sub-questions such as what is the appropriate input specification that is required to describe a processor in a way that is natural for processor designers to express and explore different hardware designs. Another important sub-question
is how should this software tool represent the processor design internally to allow it to verify the correctness and functionality of the design as well as optimize it. The novel methodology developed in answering these questions is improving a processor designer's workflow by giving them the ability to quickly have this tool synthesize
correct and optimal hardware of their intended design, rather than manually implement a potentially error prone design. Additionally identifying an appropriate formal specification of the processor system that allows processor designers to express hardware designs would be another novel contribution. Determining the appropriate
analyses and synthesis procedures a synthesis tool needs to perform is another novel engineering methodology this would contribute towards.
University of Edinburgh
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