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Active STANDARD GRANT National Science Foundation (US)

SBIR Phase I: High-Precision Timing Devices for Research and Industry

$3.05M USD

Funder National Science Foundation (US)
Recipient Organization Main Engineering Llc
Country United States
Start Date Apr 01, 2025
End Date Jun 30, 2026
Duration 455 days
Number of Grantees 1
Roles Principal Investigator
Data Source National Science Foundation (US)
Grant ID 2507531
Grant Description

The broader impact/commercial impacts of this Small Business Innovation Research (SBIR) Phase I project is in developing timing devices with increased performance and capability. These timing devices, capable of picosecond accuracy (a trillionth of a second), enable nuclear physics research, light detection and ranging, and medical imaging. This project will develop a time-to-digital converter (TDC) with unique features and the capability to operate in harsh environments.

A TDC is an electronic device that measures time intervals with extremely high precision and converts the measured time into a digital value. TDCs are widely used in applications requiring precise timing, such as LIDAR, high-energy physics, medical imaging, and communications. The market opportunities and the competitive advantage are secured through an architecture that overcomes the limitations of current TDC implementations.

The developed TDCs will be semiconductor chip based that will be fabricated domestically and introduced to three primary markets: nuclear physics, spacecraft instrumentation, and medical imaging devices.

This Small Business Innovation Research (SBIR) Phase I project is a high-availability TDC that features zero dead-time, unlimited multi-hits, picosecond accuracy, and a dedicated calibration circuit. A proof-of-concept already exists, and a prototype application-specific integrated circuit is ready for fabrication. Phase I addresses research and development of hardware and software and overall robustness to withstand high radiation and cryogenic temperatures.

This will be achieved through an iterative design methodology between logic design, transistor design, and transistor layout, each in their respective software environment. At the conclusion to Phase I, the primary goal is to have a second prototype ready to send to a chip fabrication facility. This prototype will include new features of the design, as well as radiation hardening.

The radiation hardening will allow the prototype to operate in a more extreme environment, dictated by the operational constraints of the end users. The secondary goal will analyze the extreme temperature and radiation environments of the particle physics community and determine if and how to migrate the design to a chip fabrication process that includes radiation hardening and cryogenic models for a potential Phase II follow on.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

All Grantees

Main Engineering Llc

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