Monolithic Three-Dimensional Integrated Circuit Technology Based on High-Performance Junctionless Transistors Built on Single-Crystalline Silicon Nanomembranes

The information revolution is largely driven by semiconductor industry’s capability of incorporating electronic device components in microprocessor chips with increasingly higher density, as described by Moore’s law, during the past 70-years. However, it has become more and more difficult to sustain this progress by further reducing the size of each transistor since the lateral dimension scaling is approaching its physical limits.

This project aims to address this challenge by developing a set of enabling technologies for the vertical stacking of high-performance silicon devices in future integrated circuits. This three-dimensional (3D) stacking approach allows us to achieve higher device integration density without reducing the size of individual transistors and enables a higher communication bandwidth with lower energy consumption between circuit blocks for better performance.

This project serves the U.S. national interest in helping US-based semiconductor companies to sustain their technology leadership in the worldwide competition through accelerated technology transfer. It also provides summer research internships for high-school students and develops research-based laboratory modules for the enrichment of undergraduate curriculum.

Monolithic 3D integrated circuits offer multiple advantages over conventional planar 2D architecture or 3D systems realized via wafer or chip stackings. However, their implementation and manufacturing face the fundamental challenge of forming high-performance n- and p-channel transistors on top tiers under the constraint of limited thermal budget to preserve the bottom-tier devices and interconnects from degradation.

Low-temperature processed transistors built on laser-annealed poly-crystalline silicon, metal oxides, and low-dimensional nanomaterials have been explored as potential candidates, but their performance is far inferior to transistors built on single-crystalline silicon. The objective of this research is to fill this technology gap by developing a process to transfer-print ultrathin (<10 nm thick) single-crystalline silicon nanomembranes with uniform doping on wafer scale at low temperature (<200 oC) on top of a silicon-CMOS wafer with completed devices and interconnects.

The transferred silicon nanomembrane is then utilized to build high-performance junctionless transistors without extra doping process to stay within a limited thermal budget <400 oC. They will connect with the bottom-tier transistors through ultra-dense interlayer vias to form functional logic and memory circuits with performance and chip-area footprint unattainable in 2D architectures. This project will enable a breakthrough in realizing high-performance 3D monolithic integration, overcoming thermal constraints associated with both the formation of high-mobility semiconductor layers and the fabrication of high-performance transistors.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.