CAREER: High-Level Synthesis and Compilation for Domain-Specific Reconfigurable Heterogeneous Systems

As the complexity and diversity of modern computing workloads grow rapidly, existing computer systems with homogeneous processors or accelerators show critical limitations in computing these complex workloads. This urges the creation of next-generation heterogeneous hardware acceleration systems with diverse processors and accelerators – e.g., central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), neural processing engines, etc. – as well as their design automation and programming tools.

However, existing heterogeneous computing systems face the "diversity crisis" where the heterogeneity of systems poses critical challenges on the system design and optimization. This project aims to mitigate these challenges by developing an efficient compilation and synthesis flow that compiles high-level programs into domain-specific reconfigurable heterogeneous acceleration systems.

The design productivity improvement from this project can potentially mitigate the hardware design workforce shortage problem that society currently faces, and it can directly translate into a larger semiconductor market and increased domestic job openings. The advancement in hardware acceleration can innovate scientific discovery, artificial intelligence, and other fields.

The education activities in the project can improved the skill sets of future semiconductor workforce.

The objective of this project is to develop an efficient compilation and synthesis flow from high-level programs (e.g., Python) to domain-specific reconfigurable heterogeneous acceleration systems. This project aims to create a framework that features the following key innovations: (1) a heterogeneous and efficient acceleration system template that combines hardened digital accelerators, reconfigurable digital logic, and general-purpose processors; (2) an optimizing compiler and an agile design automation flow that partition and compile high-level application code, and generate the optimally configured heterogeneous hardware system design and programs; (3) a hardware-aware learning-based optimization engine that constructs global design spaces and searches for the optimal configuration of the heterogeneous system and program that meets application requirements; and (4) the optimal runtime scheduling of the computing tasks and runtime dynamic reconfiguration of the programmable logic elements inside the heterogeneous system.

This project focuses on the fundamental research in electronic design automation (EDA) tools, and it is expected to accelerate the development of modern computing systems and design methodology.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.