CAREER: Optimizing the Next Frontiers of Chiplet-based Designs in Advanced Packaging

Modern Artificial Intelligence (AI) workloads demand computing systems with large silicon areas to sustain throughput and performance. However, manufacturing costs, yield limitations at advanced tech nodes, and die sizes reaching the reticle limit restrain us from achieving this on a monolithic die. With the recent innovations in advanced packaging technologies, disaggregated chiplet-based architectures have opened the next frontier of innovation in AI hardware and System on Chips (SoCs).

However, the scope of stacking multiple chiplet tiers in 3D, various package interconnect options, and thermal challenges introduce significant design challenges. The project’s key novelties are developing AI/Machine Learning(ML)-assisted System and Package-level co-design methodologies that can optimize the power, performance, chip area, reliability, and cost of the next-generation AI hardware.

The project's broader significance and importance include: (1) Generate knowledge and scientific methods to optimize the system-level architecture of multi-tier chiplet-based designs, and thus contribute to the advancement of the field of AI hardware and AI. (2) Develop educational resources and open-source tools for designing next-generation chiplet-based hardware in advanced packaging. (3) Cultivate a pipeline of skilled engineers and scientists with expertise in computer systems and AI/ML, and to promote participation from undergraduates, underrepresented groups, and K-12 students.

In Thrust 1, using the first principles, the key performance metrics of chiplet-based AI hardware are analytically modeled. Heuristics and deep learning (e.g., Reinforcement Learning) based methods are explored to find the set of optimal parameters (e.g., chiplet area and count, number of tiers, packaging interconnects, etc.). Thrust 2 focuses on yield, reliability, and power integrity.

Hardware and software-level comprehensive techniques are developed to detect and repair faulty Hybrid Bonds (HB) to achieve maximum yield at the package level. To ensure robust power integrity of the multi-tier chiplet system at optimum energy efficiency, the emerging technique of backside power delivery is explored. As heat dissipation is a major impediment to the widespread adoption of multi-tier chiplet stacking technology, Thrust 3 explores a proactive thermal management technique and workload scheduling algorithm to prevent simultaneous peak temperatures in adjacent chiplets in a stack.

Overall, the collective advancement of these research thrusts will establish a comprehensive scientific methodology for the design of multi-tier 3D SoCs.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.