SHF: Small: Enhancing Performance and Reliability in On-Chip Power Distribution Networks

Today’s world is increasingly driven by advanced electronic integrated circuits, or chips, which power artificial intelligence (AI), infrastructure, mobile communications, scientific computation, and consumer electronics. The computations in a chip are facilitated by supply voltages that are distributed to the computational elements through power distribution networks (PDNs).

These PDNs consist of structures that carry large currents through lossy filamentous wires, which may be inadequate for ensuring robust voltage levels at the computational elements. These effects can potentially lead to incorrect computations and unacceptable errors. Moreover, high currents can cause accelerated aging in the PDN due to phenomena such as electromigration (EM) that can result in chip failure.

Developing optimization strategies that ensure supply voltage integrity and PDN reliability is therefore critical. The task is further complicated with the challenges associated with emerging methods for building advanced integrated circuits, including new wire and transistor structures, and elevated on-chip currents and temperatures that degrade performance and reliability.

Therefore, the development of PDN design techniques is vital for enabling the next generation of chips that drive computation from the datacenter to the edge.

This project aims to address the challenges of optimizing voltage drop and EM in PDNs, while ensuring minimal utilization of the limited available on-chip wiring resources. For the problem of voltage drop, the work will address today’s widely used front-side interconnects as well as newer backside interconnect technologies. Degradations in supply voltages can also cause circuit delays to deteriorate: the interplay of PDN optimization on circuit timing in digital circuits will be addressed in this project through new approaches that break down the barrier between PDN design and timing optimization, performing integrated optimizations that benefit both PDN resource usage and logic circuit metrics.

To address EM, this research will advance the use of physics-based approaches that predict chip lifetimes by directly modeling EM-induced stress in interconnects. New methods will be developed based on a stress-electrical duality that maps accurate physics-based stress analysis to methods for analyzing resistor-capacitor (RC) networks and transmission lines.

An educational component of the project aims to attract fresh talent to advance the mission of workforce development in the field of electronic design automation. Specific efforts will target students at the K-12, undergraduate, and graduate levels, and intend to attract women and other underrepresented minority groups. Outreach activities will be centered around artificial intelligence and semiconductor technologies, and will be supplemented by curriculum development efforts.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.