NSF Workshop on AI for Electronic Design Automation

Advanced integrated circuits (ICs), also called computer chips, consist of over 100 billion transistors in sub-5 nanometer fabrication technologies and are arguably one of the most complex human-made objects created in human history. Their design and manufacture are enabled by a set of sophisticated Electronic Design Automation (EDA) tools that support the automation of design creation, synthesis, simulation, test, and verification processes so that the engineers can keep up with the exponential growth of design complexity following Moore’s Law.

Beyond the general-purpose processors, in the past few years, domain-specific accelerators (DSAs), such as Google’s Tensor Processing Unit, have shown to offer significant performance and energy efficiency over general-purpose Central Processing Units (CPUs.) However, domain-specific accelerators still require deep hardware knowledge to achieve high performance. Leveraging artificial intelligence (AI) techniques to further automate chip design becomes the key to meeting the needs of broad applications, which is also critical for democratizing hardware design and creating next-generation energy-efficient hardware.

This project supports a workshop co-organized by experts from two different fields, machine learning (ML) and EDA. The workshop will be co-located with a premier ML conference, the Conference on Neural Information Processing Systems (NeurIPS). It will bring researchers and practitioners from both ML and EDA communities to discuss how AI can address challenges in different stages of hardware design, promoting open benchmark datasets and open discussions to revolutionize chip design.

DSAs are hard to design and require deep hardware knowledge to achieve high performance. The challenges are twofold. First, it is time consuming for the existing tools to evaluate the performance of different designs.

This makes it difficult for the existing design space exploration tools to evaluate a sufficient number of design points to generate a high-quality solution. Second, even though one can predict the performance for any design point efficiently and effectively, it is still hard to design a search algorithm to optimize the design points. In fact, such optimization problems arise in all stages of EDA, including high level synthesis (HLS), register-transfer level (RTL)/logic synthesis, and physical designs, which can all benefit from various ML techniques.

This workshop aims to bring in researchers with diverse backgrounds and experiences to have an in-depth discussion on these challenges. It includes several major activities: (1) calling for research papers from different stages of automating chip design; (2) inviting speakers from both machine learning and chip design, and both industry and academia, to address the joint community; (3) organizing panel discussions and round table discussions to shape this field and providing a workshop report to the National Science Foundation; (4) holding an HLS contest; and (5) promoting benchmarks in chip design which are key to the success of leveraging AI technology.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.