NQVL:QSTD:Pilot: Accelerating Fault-Tolerant Quantum Logic (FTL)

The ability of quantum hardware to outperform classical hardware for tasks like computation, communication, and sensing is known as quantum advantage. Quantum advantage promises society-changing benefits including fundamentally secure communication, improved biomedical sensing, and breakthroughs in material and drug design. To date, useful quantum advantage for computation has not been realized.

Though there is reason to be optimistic for near term advances, it is widely accepted that useful quantum advantage in computing will require fault tolerance at scale -- an advance that is still beyond the reach of current devices. This project is aiming to accelerate the development of fault-tolerant quantum computation by co-designing error correcting codes and the hardware that will run them.

Currently, many quantum error-correcting (QEC) codes have been discovered, and their mathematical structures are becoming better understood. Meanwhile, hardware with a few logical qubits has been demonstrated and, in some cases, a small gain in process fidelity realized. However, the demands on hardware for current QEC codes are severe -- either enormous numbers of qubits are required or native gate fidelities must be extremely high (often, both).

By designing QEC codes to utilize the native gates and connectivity of the hardware, while simultaneously optimizing the hardware layout to support the QEC code, fault tolerance can be achieved with the minimum resource cost thereby delivering useful quantum advantage sooner.

Of the existing hardware platforms, the trapped-ion QCCD architecture shows a special promise to achieve fault tolerance, especially in view of the recent progress where key problems such as qubit shuttling and wiring have been solved. Further, it currently provides the highest state preparation, measurement, and gate fidelities, and has led to commercial systems with the highest quantum volume.

It also natively provides mid-circuit measurement with minimal cross-talk error and has a well understood error model. Finally, it provides all-to-all qubit connectivity. These features are likely to be necessary requirements for realizing fault tolerance in the near term.

To accelerate progress in fault-tolerant quantum computing, an interdisciplinary team composed of computer scientists, engineers, physicists, and educators focuses on the identification of the most efficient QEC codes for the hardware and the optimization of their deployment on the QCCD system. Further, they research how to improve gate fidelities while working closely with commercial vendors to realize the assembly of such a fault-tolerant QCCD system.

Finally, the team convenes a community of educators, industry and government leaders to chart the optimum route for meeting the workforce needs of the field.

This project advances the objectives of Quantum Information Science and Engineering at NSF in response to the National Quantum Initiative Act for the continued leadership of the United States in QIS and its technology applications.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.