SHF: Small: Understanding Correctness and Efficiency in Hardware Accelerators

Custom, domain-specific hardware accelerators are critical tools for advancing computationally intensive applications in the modern era of computing. While a new generation of accelerator design languages (ADLs) has raised the level of abstraction for designing specialized hardware, architects must also rely on analyses beyond the language itself to optimize performance and identify and fix correctness issues.

This project will develop techniques for efficient debugging and profiling of accelerator designs, which will in turn reduce the time and cost of developing efficient hardware to support applications that require more performance than general-purpose hardware can offer. The project will also support a new cross-institutional community for industry and academic collaboration on open-source projects for ADLs and their associated tools.

This project will focus on three main techniques for understanding the performance and correctness of accelerator designs. First, it will develop methods for collecting actionable data on three key efficiency metrics: resource consumption (i.e., area), critical timing paths (which determine the hardware's maximum clock frequency), and cycle-level timing.

These techniques will be embodied in a tool that generates flame graph visualizations of these metrics, relating them to programmer-visible constructs. Second, the project will create a new method for combining the deep observability of software simulation with the sheer execution speed of field programmable gate array (FPGA) emulation. This involves collecting lightweight snapshots of executions running on a real FPGA and transferring this execution state to software emulation for detailed inspection.

Finally, the project will design mechanisms to understand concurrency bugs by exposing issues arising from the interleaving of parallel events in accelerator executions. A new method will be developed to systematically manipulate an accelerator's execution schedule at runtime, searching for schedules that reveal buggy behaviors. This will lead to a deeper understanding of how concurrency affects the correctness of accelerator designs.

This project is jointly funded by the Software and Hardware Foundation (SHF) core research program and the Advancing Informal STEM Learning (AISL) program.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.