Via Critical Dimension Metrology by Grayfield Imaging Interferometry

A nontechnical description of the project:

This project investigates experimental and computational approaches to the characterization of geometric and optical properties of the vias, establishing a new via metrology and inspection technology for advanced wafer-level packaging (WLP) that enables three-dimensional (3D) heterogeneous integration (HI). With the advent of high-performance electronic devices used in automotive, airplanes, computers, cellphones, televisions, or tablets, the semiconductor industry is looking for high-throughput, reliable, low-cost manufacturing, and inspection technologies of micro/nanoscale vias on circuitry and wafers to achieve advanced WLP.

Semiconductor industry must have via metrology and inspection technology for the ongoing trend of miniaturization and integration of electronic devices. Vias on the electronic devices are copper-lined holes that enable a 3D electrical interconnection between the different layers of the circuitry. Vias on the silicon, flexible printed circuit board (PCB), or glass wafers are in the range of diameter 5~100 µm and depth 100~200 µm.

Even a single via defect on the device can impact multi-layer chip stacking and prevent the vias from enabling electrical interconnection between the circuit layers. As the via size gets smaller and smaller, via parameters such as diameter, roundness, via-to-via distance, heat-affected zone, and via-edge roughness should be monitored and controlled.

Additionally, even if the different layers are stacked somehow with defective vias, the performance of manufactured chips is not guaranteed, and there could be issues in signal integrity, reliability, thermal management, etc. Hence, via metrology and inspection are essential technologies in WLP. However, current via metrology is limited to assessing via geometry by conventional microscopy because via critical dimension (CD) decreases in the nanometer scale.

The proposed transformative research will enable the inspection, metrology instrumentation, and in-situ analysis that not only benefits the electronics industry with emphasis on quality control but also enables the via manufacturing processes under tight control, quality improvement, and reduced scrap rates to enhance environmental sustainability. In addition to technological advancement, this project will educate future scientists and engineers in semiconductor engineering, raising awareness for semiconductor engineering workforce development at the university level, broadening a knowledge base, and promoting research and education engagement in academic communities.

Advancements in semiconductor metrology, inspection and instrumentation technology will influence U.S. semiconductor technology and strengthen the U.S. industry and job market by upskilling the U.S. semiconductor engineering workforce. A technical description of the project:

This research will reveal new knowledge and research paradigms in via metrology, design, light-matter interaction, and manufacturing by creating rapid modeling methodologies for the inspectability of various types of defects on vias to prevent catastrophic failures in complex WLP processes. Also, the experimental/computational modeling and calibration methods for the via property characterization will be introduced.

This project (1) establishes a via-edge topography model to characterize its geometry (diameter, roundness, position, and via-edge roughness) and its scattering behavior by the proposed metrology system (grayfield imaging interferometric microscopy) and light-via computational models, (2) characterizes light-via interactions according to the corresponding changes in via edge topography, and (3) confirms the relationship between the via geometry and the corresponding optical property changes for via defectivity metrology and inspection. Through-focus scanning microscopy (TSOM) that stacks interferograms along the via depth direction will be to validate the computational approaches for enabling 3D via characterization.

The successful completion of the proposed research will provide a novel approach to via defectivity metrology, design, models, and manufacturing. The outcomes of this project will provide the via CD defectivity database that the common types of via defects and their root causes can be identified. This result enables the semiconductor manufacturing process control, especially for WLP, in a new aspect, allowing the wafer handling processes to be under tight control and improving yield.

The research team envisions a near future where HI chips, microelectronics devices, or systems significantly improved by emerging metrology, inspection, and instrumentation will leverage chip manufacturing process capabilities for high volume and high throughput production. Also, the outcomes of this research will have a great impact not only on semiconductors but also on materials chemistry, physics, and optics.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.