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| Funder | National Science Foundation (US) |
|---|---|
| Recipient Organization | University of California-Riverside |
| Country | United States |
| Start Date | Oct 01, 2024 |
| End Date | Sep 30, 2027 |
| Duration | 1,094 days |
| Number of Grantees | 1 |
| Roles | Principal Investigator |
| Data Source | National Science Foundation (US) |
| Grant ID | 2426161 |
Heterogeneous hardware architectures (including graphics processing units, field programmable gate arrays, and application-specific integrated circuits) are shaping the future of computing and artificial intelligence (AI) acceleration. However, the use of such extraordinary computing power from heterogeneity is restricted to a limited pool of software developers with deep microprocessor expertise.
Although high-level synthesis (HLS) compilers have been developed to convert computation logic written in high-level programming languages to low-level register transfer level based kernels, this process requires significant code rewriting to meet synthesizability and performance requirements. To improve developer productivity in this emerging domain, this project develops new automated code transpilation, testing, and debugging technologies to lower the barriers of developing heterogeneous applications, thereby making emerging hardware accessible to software engineers with different levels of hardware expertise.
This project will also train the technology workforce with interdisciplinary computing backgrounds in software engineering, hardware design, heterogeneous architecture, and compilers.
Specifically, this research has three innovative components. First, it will design efficient program transformation and interactive design exploration methods for porting classical software that targets central processing units (CPUs) to its heterogeneous version with behavior preservation and optimized performance. Second, it will design new automated testing methods for heterogeneous applications that obtain increased visibility with new hardware-level probes and adapt existing tests to various platforms.
Third, it will design automated debugging methods for source code tracing and pinpointing the root causes of failures throughout a multi-phased hardware compilation process. In summary, this project will produce a suite of advanced open-source debugging and testing tools as a key enabler for harnessing the potential of hardware heterogeneity.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
University of California-Riverside
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