FuSe2 Topic 3: SPRINT: Scalable, High Performance and Reliable Interconnect Technologies based on Interface Co-Design

Nontechnical Description

Interconnects are layers of metal conductors with nanoscale to microscale dimensions that connect different electronic devices in a computer chip. Copper is the standard for its abundancy, low cost and good electrical conductivity. However, when its dimensions are reduced below 10 nanometers, its resistivity increases dramatically.

As a consequence, power consumption and heat generation increase dramatically. This scaling trend for copper interconnects has two causes. First, electrons in ultrathin copper nanowires can no longer move freely due to structure and property changes.

Second, the surface of copper nanowires must be encapsulated with an insulating layer to make the structure more stable, but this further reduces charge transport. This project aims to develop a new way to synthesis copper nanowires and design effective encapsulation layers based on two-dimensional materials. These break the paradigm limiting current interconnect technology and enable next generation high-performance and energy-efficient computer chips.

Research in this highly interdisciplinary project is integrated with education and workforce development. The project engages students at all levels, providing training in physics, materials science, and nanoelectronics. Investigators closely collaborate with industry, government, and education partners to cultivate future technology leaders and incubate technology transfer.

Technical Description

In modern microchip technologies, aggressive downscaling of the logic, memory, and interconnect components is crucial. Conventional interconnect technologies based on polycrystalline Cu face the following fundamental downscaling challenges: (i) the resistivity increases drastically as its linewidth is decreased due to electron scattering at the metal/insulator interfaces and grain boundaries; and (ii) the interfacial liners and barriers around Cu wires are essential to avoid the ionic diffusion across the metal/insulator interface, but these additional non-conductive structures further compromise the downscaling capability.

This project aims to establish a multidisciplinary and closed-loop co-design framework to facilitate the investigation of the chemical and atomic structure at the metal/insulator interface and its electronic and ionic transport properties and to enable advanced interconnect applications that are scalable, high-performance, and reliable. Precise control of the metal surface orientation and its interface with the atomically thin 2D-material-based liner-barrier are established through multiscale simulation, novel metal deposition and heterostructure integration processes, and multi-modal material-device co-characterization.

The 2D material layer encapsulated on the surface of Cu nanowires will facilitate the modulation Cu crystal surface orientation, and at the same time, serve as the ultrathin ion diffusion barrier to enhance the interconnect reliability. This project also offers potential pathways for integrating this new interconnect technologies with silicon integrated circuit chips, paving the way for upscaling such an emerging technology for industrial development and manufacturing.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.