FuSe2 Topic 2: Heterogeneous In-Package Photonics with Reconfigurable Optical Switching for AI Clusters (HEROIC-AI)

A nontechnical description:

Society is experiencing a widening gap between artificial intelligence (AI) demand and computing hardware capabilities, which must already catch up with Moore's Law. This immense hunger for computing power is driven by continuous advancements in computing hardware, which now faces the constraint of interconnect inefficiency, exemplified by the infamous “Memory Wall.” Under the Future of Semiconductor 2 program, this project proposes a highly integrated photonic chip solution to enable ultra-high bandwidth, energy-efficient data transmission between computing nodes.

The approach incorporates multiple innovative advancements across materials, devices, integration, architecture, and network topology. This collaborative research, conducted by three leading universities in partnership with four industrial IT companies and a national lab, aims to achieve a significant leap in performance metrics over current state-of-the-art technologies.

The broader impacts of the proposed research, driven by a mixture of academic and industrial veterans, also include expediting tech-to-market transfer and nurturing next-generation minds with a real-world perspective, co-designed execution flow, and practical know-how build-up. The effort ensures a holistic approach to education and innovation. Participated student researchers will heavily benefit from and further propel various regional and national semiconductor training and research programs.

A technical description:

The project aims to develop a novel system-in-package technology with a heterogeneous multi-functional in-package photonic platform/interposer, accommodating CPUs, TPU, or GPU (collectively, Processing Units (PU)) chips, high-bandwidth memory (HBM) stacks, and accelerator/ASIC chips, etc. Each PU and HBM chip is intimately integrated with a heterogeneous optical transceiver, composed of ultra-compact high-speed modulators and photodetectors, which provide up to 400 Gb/s/lane communication bandwidth.

Arrays of 200-400 Gb/s heterogeneous modulators support a record-large 9.6-19.2 Tb/s total communication bandwidth for each PU chip. Moreover, the project will develop on-chip lithography-free photonic routing circuits and heterogeneously integrated waveguide-free optical switches with optical gain to enable reconfigurable on- and off-chip optical switching networks that can be dynamically programmed to realize various network topologies for different AI algorithms.

The hardware platform will be developed with seamless co-design of materials, devices, fabrication, system, architecture, and network topology and benchmarked with an automatic network mapping framework.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.