CMOS+X: Novel Gate-Stack Engineering for 2D Materials-Based FETs

Silicon (Si) based metal-oxide-field-effect transistors (MOSFETs) have powered the tech industry for decades, but their improvements in performance and energy efficiency are slowing down. This has led scientists to explore new materials to keep up with the demands of Moore's law, which predicts the doubling of transistors on a chip every two years. One promising alternative is two-dimensional (2D) semiconductors (2DS).

These materials are incredibly thin, have smooth surfaces, and provide excellent control over electrical properties. However, there are several challenges to overcome before 2DS can compete with silicon. Unlike silicon, 2DS lacks a natural oxide layer to ensure a clean and efficient interface with the gate-oxide, which is crucial for high performance.

Additionally, because 2DS materials don't have out-of-plane bonds, it’s difficult to directly grow any conventional high-k dielectrics (like HfO2 and ZrO2) on them. This necessitates finding alternative gate-dielectric strategies to meet the International Roadmap for Devices and Systems (IRDS) gate-leakage requirements.

The PI is a pioneer in the field of 2DS based FETs and has made major contributions to every aspect of these transistors. Recent theoretical studies by PI’s team have identified some 2D high-k dielectrics, which could be ideal as an interfacial oxide layer for 2DS FETs. By combining monolayer or bilayer of such 2D high-k dielectrics with conventional high-k dielectrics, one can create an ideal gate-oxide stack.

This combination is expected to achieve the desired nanoscale-FET characteristics and meet the IRDS specifications. This project aims to thoroughly understand such 2D high-k dielectric materials through a combination of theoretical and experimental approaches. This interdisciplinary research could lead to the discovery of new interfacial dielectric layers for 2DS, potentially replacing Si in advanced technology.

This project has the potential to impact a wide range of electronic products that use FETs, including microprocessors and memory devices. Consequently, its outcomes could significantly influence the semiconductor and electronics industries. The PI plans to use established educational platforms to share the research findings broadly, making them accessible to a broad audience.

The project also integrates research with education across all levels, from K-12 to undergraduate and graduate students. This will be achieved through participation in educational programs and initiatives aimed at recruiting and retaining a broad range of students in nanoscience and engineering.

This project addresses the design, fabrication, reliability, and performance challenges of 2DS FETs using a novel 2D high-k /3D high-k dielectric gate stack. Significant advancements over the existing gate oxides are proposed by developing a comprehensive simulation framework, spanning density functional theory (DFT) at the material level to non-equilibrium Green’s function (NEGF) at the device level.

The simulation framework will provide feedback to improve and optimize the overall device performance. Necessary test-structures (Metal-insulator-metal, metal-oxide-semiconductor (MOS), and MOSFETs) will be fabricated, and various optical, structural, and electrical characterizations will be carried out to inspect the quality of the materials and gate stack, which will serve as feedback for further optimization of the materials growth processes.

The proposed project is transformative as it stands to revolutionize a multitude of applications by identifying and addressing the scientific and technical barriers to high performance 2DS-FET nanomanufacturing. The proposed research not only ushers an era of high-performance, low-power, and energy-efficient 2DS-FETs, but also has the potential to revolutionize the semiconductor, electronics, and computing industries, leaving a profound impact on society at large.

This project was jointly funded by the Electronics, Photonics, and Magnetic Devices program, Division of Electrical, Communications and Cyber Systems (ECCS), Directorate for Engineering, and the Electronic and Photonic Materials program, Division of Materials Research (DMR), Directorate for Mathematical and Physical Sciences.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.