Collaborative Research: SaTC: CORE: Medium: Pentimenti - Securing Cloud FPGAs from Analog Temporal Side Channels

Cloud service providers offer Field Programmable Gate Arrays (FPGAs) as a time-shared service for efficiently accelerating high-value workloads such as machine learning, genome sequencing, databases, encryption, and other applications with strict security requirements. While the hardware is time-shared between multiple tenants, there is generally believed to be no information leakage between subsequent users since the FPGA bitstream and memories are digitally erased after each tenant’s use.

The project studies “FPGA pentimenti” data that leaks between subsequent users through analog effects. The project’s broader significance and importance are developing techniques for securing cloud infrastructure and promoting education and research in FPGA security.

This project studies, characterizes, and develops mitigations for FPGA pentimenti. Specifically, this project investigates how data from previous users is leaked via an analog side channel due to bias temperature instability effects. This project establishes bounds of data-recovery capabilities within the cloud FPGA model and identifies effective defenses for all stakeholders.

This project also characterizes techniques for extracting FPGA pentimenti. With this knowledge, this project develops mitigations to reduce or eliminate these analog side-channel attacks from the perspective of the manufacturer, cloud provider, and end-user.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.