GOALI: ASCENT: Wafer-Scale Computational System (WaSCoS) with heterogeneous integration, power-heat transport, and optical interconnects

Wafer-scale systems have the potential to condense a rack's worth of electronics into a single wafer along with a much lower carbon footprint. This proposal seeks to explore and demonstrate technologies needed to make this potential a reality. The main technology of concern will be fine-pitch heterogeneous integration, wherein a great number of very small and diverse (i.e. heterogeneous) electronic parts (so-called chiplets or dielets) are interconnected very closely together; the number of connections between the chips is about 10 to 100 times more than today’s conventional systems.

These two features allow for shrinking the footprint of the system considerably. Traditional printed circuit boards are replaced by large silicon wafers and coarse soldered connections will be replaced by microscopic solderless welded connections that are 10 to 100 times denser. The compact nature of such systems means that more power needs to be delivered in a smaller space and more heat needs to be extracted from a smaller space.

The immense computing density possible with this system requires new methods of moving data in and out of the system using precision micro-aligned optical fibers combined with high density electrical connectors. This technology will take off where Moore’s law for chips leaves off and allow for sustainable scaling of computing capabilities. The development of these technologies will also provide a valuable and practical learning vehicle for our students that will be needed for the manufacturing resurgence that is planned for packaging and semiconductor technology and will also flow into existing outreach programs to attract high school students organized by UCLA faculty to STEM fields.

The project aims to produce a system wherein dies are assembled on Si-IF to pitches of sub-10-μm (compared to 500-μm ball grid array (BGA) pitches on a traditional printed circuit board). The wiring pitch on the Si-IF will be sub-μm, compared to the tens of μm typically seen on a PCB using precision aligned thermal compression bonding. This permits the packaging of heterogeneous dielets (processors, memory, communication chips, etc.) with very high bandwidth, low latency, and low energy per bit - well beyond the metrics of even the most advanced silicon interposer packaging approaches today.

Ideally, such an approach will allow near 10-TB of uniformly accessible memory with bisection bandwidths near 75x larger than today’s systems, an aggregate bandwidth increase of about 250x and a uniform latency reduction of about 40x. Such results could support unprecedented workloads in computing. Aside from die assembly, challenges to this goal include architecture and design infrastructure needs for synthesizing such a system; power delivery and thermal dissipation solutions able to both provide the projected  25-kW required by such a system and safely and efficiently extract a similar amount in heat; and wavelength division multiplexing approaches capable of delivering up to 20-100 Tb/s of data while conforming to a sufficiently small form factor using a flexible fan-out wafer-level packaging approach titled "FlexTrate."

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.