FET:Small: An Integrated Unipolar-0.5T0.5R RRAM Crossbar Array for Neuromorphic Computing

The processing capabilities of the human brain are unparalleled compared to what is achievable with conventional computing techniques, particularly for applications targeted toward pattern recognition, and needs dedicated hardware to be emulated. Neuromorphic (NM) computing hardware, which aims to mimic these neuro-architectural aspects of the human brain by having the memory- and processing-centers co-located (compute-in-memory), can deliver processing and computations on an energy scale that is orders of magnitude more efficient than the conventional von-Neumann architecture where data are transferred between separate memory and processing elements.

Therefore, NM computing can enable significant computational advances for a variety of real-world applications. The compute-in-memory hardware is typically implemented using a crossbar array layout of resistive random-access memory (RRAM) devices, where each memory device is connected in series with a control transistor, in what is commonly referred to as a one-transistor one-resistor (1T1R) cell format.

Although this format ensures the memory devices work reliably and efficiently, it increases the device count and circuit area. The PI has recently demonstrated a novel "0.5T0.5R" memory cell architecture where a control device - a transistor - and a memory element - a RRAM - are integrated into a single hybrid device by judicious use of two-dimensional (2D) materials with resulting substantial improvements in the scaling, density, and device/circuit performance.

The three-year project involves the design, fabrication, and characterization of crossbar arrays of these devices to implement compute-in-memory hardware, thereby enabling demonstration of large-scale NM computing circuits. The application space of NM computing is targeted towards both machine learning and pattern recognition and can be used in a multitude of real-world applications not limited to self-driving cars and big data, thereby enabling a much broader scientific impact.

Moreover, significant improvements in the energy-efficiency of NM and in-memory computing paradigms will enable their wide-scale deployment and enable computing hardware to keep pace with the rapid growth in data intensive applications in spite of CMOS technology scaling limitations. Thus, the project is expected to have wide implications for the semiconductor and electronics industries.

Moreover, the PI will use various well established educational platforms to disseminate the research results and to make them available to a wide range of users. The overall project also ties research to education at all levels involving K-12, undergraduates, graduates, and minorities, partly via participation in programs designed by education professionals, besides focusing on recruitment and retention of underrepresented groups in nanoscience and engineering.

This project involves the conceptualization, design optimization, and hardware demonstration of novel and energy-efficient neuromorphic/in-memory computing circuits enabled by innovative large-scale crossbar array implementation of a novel 0.5T0.5R memory device. Experimental work is being carried out with close modeling and simulation support to optimize the device and array design.

More specifically, development of compact models with the aid of numerical and ab-initio simulations to help in device optimization and developing neural learning algorithms, to be subsequently implemented in the crossbar array, is being carried out in tandem. The interdisciplinary nature of the research project, spanning fundamental 2D materials science, device design, and nano-fabrication techniques, as well as theoretical simulations and system architecture design, ensures that the proposed research ideas are feasible and tailored to deliver optimal neural learning and inference objectives.

Significant improvements over recently demonstrated NM computing devices are proposed, employing large-area 2D materials synthesis techniques and configuring the hybrid device to provide further scalability and ease of energy-efficiently addressing array elements. Finally, hardware neural tasks pertaining to real-world applications of pattern recognition, cybersecurity, and implementing physically unclonable functions are being demonstrated.

The successful completion of this project is intended to advance the development of a revolutionary new class of NM computing systems that efficiently emulate biological information processing.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.