Collaborative Research: SHF: Small: Programmable Hierarchical Caches: Design, Programming, and Prototyping

As computing technology becomes ever more powerful, memory is larger but more complex, with different materials, configurations, and interconnects having different trade-offs among capacity, speed, and cost. Because of this complexity, fully automatic solutions are increasingly sub-optimal and brittle. This project develops new designs of the memory hierarchy that are programmable and therefore can achieve better performance and provide stronger guarantees than conventional solutions used on current computer systems ranging from smartphones to supercomputers.

The new programmability enables optimization in software and hardware in concert. Since computer cost and speed depend on memory hierarchy, programmable designs can overcome the current limit in scalability and power efficiency. Beyond its technical content, the project advances teaching in the science of computer memory and strives to increase the diversity among participants in this area of research and development.

Specifically, the project develops a two-level programmable cache system called the lease cache and designs its programming techniques. It has three parts: automatic programming and optimization of the lease cache; hardware design and prototyping of a RISC-V processor with the two-level lease cache on an FPGA board; and lease-cache theory especially statistical properties and guarantees of the cache performance.

Through theories and prototyping, the new designs can retain software portability, ensure matching performance to current automatic solutions by default, and provide precisely defined cache performance properties.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.