SHF: Small: Research on Standard Cell Layout to Facilitate the VLSI Technology Scaling

Physical layout plays an essential role in the scaling of VLSI technology nodes. As the whole VLSI industry tries to sustain technology scaling, the paradigm is shifting from geometric scaling to design technology co-optimization, and soon to system technology co-optimization. The paradigm shifts require the advancement of physical-layout techniques to tackle the new problems related to sustaining the scaling of the technology.

The project works on the advancement of standard cell layout in terms of analysis, synthesis, and optimization to embrace the demand of the design technology and system technology co-optimization. The objectives are to facilitate the scaling of VLSI technology nodes. The approach is to perform system and design co-optimization in the domain of physical layout.

The outcome would benefit the whole VLSI ecosystem including consumers, markets, and research and development. The project is facilitating the advising of a diverse group of graduate and undergraduate students including minority, female students, and students under adverse circumstances.

The research of technology scaling is focusing on four thrusts. (1) Routing analysis and unrouteable case diagnosis: The study analyzes the VLSI routeability and diagnoses the cause of the unrouteable cases to embrace the increasing complexity of the conditional design rules. (2) Library cell layout synthesis: The research automates the library standard cell layout to facilitate the technology scaling. (3) Design and system technology co-optimization with pitch scaling: The research facilitates design and system technology co-optimization with pitch scaling. (4) Extension of CMOS technologies and beyond: The exploration studies 3D devices, new materials, and novel architectures. The project outcomes include advanced methodology, theory, and algorithms for VLSI physical layout, and software packages for a suite of layout tools.

The results are being disseminated for VLSI production via collaboration with research laboratories and technology companies.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.