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Completed STANDARD GRANT National Science Foundation (US)

CRII: SHF: Enabling Metal Inter-Layer Via Device Utilization for On-chip Memory in Monolithic Three-Dimensional Integrated Circuits

$1.75M USD

Funder National Science Foundation (US)
Recipient Organization North Dakota State University Fargo
Country United States
Start Date Jul 15, 2021
End Date Dec 31, 2023
Duration 899 days
Number of Grantees 1
Roles Principal Investigator
Data Source National Science Foundation (US)
Grant ID 2105164
Grant Description

A monolithic three-dimensional integrated circuit (M3D IC) is a promising technology to meet future computational demands as transistor density increases due to the vertical dimension. This project addresses one of the primary design challenges associated with the M3D IC technology to realize energy-efficient and compact integrated chips. The project is facilitating further advances in M3D IC technology by providing novel device models and design strategies for integrated chips to the research community.

The investigator is developing a participation plan to involve students from the underrepresented groups in the field of integrated circuits through this project. The techniques developed in this research are intended to be used to develop computer-engineering courses and also to be presented in technical seminars for industry collaborations.

In M3D IC technology, the substrate layers are realized sequentially, and these layers are connected through metal inter-layer vias (MIVs). This project aims to develop small footprint and efficient M3D IC designs by opportunistically utilizing substrate area around MIV to form MIV-devices specifically MIV-capacitor and MIV-transistor. This brings in new challenges for designing and characterizing MIV-devices to optimize the form factor and efficiency.

These challenges are addressed by this project through 1) developing SPICE models for proposed MIV-devices in M3D-IC technology, and 2) utilizing these MIV-devices for on-chip static random-access memory (SRAM) and dynamic random-access memory (DRAM) to enable compact and power-efficient M3D ICs. The techniques developed in this research are providing future opportunities for M3D IC technology at all design levels – device, circuit, and computer-aided design.

The results of this project are intended to lay a foundation for a design framework for full-scale M3D IC designs to meet future computational requirements.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

All Grantees

North Dakota State University Fargo

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