CAREER: Systems and Architectural Support for Accelerator-Level Parallelism

This CAREER research project designs software-hardware collaborative mechanisms to sustain the performance and energy-efficiency improvements in today's world where applications are increasingly deployed on chips with a wide variety of hardware accelerators. Achieving this goal requires efficiently managing the concurrent use of accelerators in an application and globally optimizing across accelerators through detecting, analyzing, and modifying the task flow and data flow in applications.

This research unlocks next-generation software innovation in emerging domains, such as augmented/virtual reality, smart sensing, and mobile robotics. The research agenda is complemented by an educational/outreach agenda. The project will: (1) promote inter-disciplinary research between CS and the Archaeology, Technology, and Historical Structures (ATHS) program at University of Rochester by helping reconstruct and render Elmina Castle, a UNESCO World Heritage Site, on mobile virtual reality devices; (2) offer undergraduate students inclusive opportunities for hands-on experience in emerging application domains and hardware acceleration; (3) re-structure undergraduate and graduate curricula to incorporate cross-domain acceleration; and (4) teach hands-on Introduction to Computing courses to students from the Vanguard Collegiate High School and Wilson High School at the Rochester City School District.

This research project breaks away from conventional research on individual accelerators. The key intellectual merit is the pursuit of mechanisms that globally optimize across accelerators. The research is complementary to improvements in individual accelerators.

The technical approach is two-pronged: 1) design mechanisms that approach the upper bound of acceleration by reducing the overhead of accelerator interaction, including inter-accelerator data communication and task coordination; 2) design systems to go beyond pure acceleration to enable algorithms that share metadata across accelerators. The research project aims to develop programming interfaces and compiler support that expose data flow, task flow, and metadata sharing opportunities across accelerators.

The language and compiler are supported by lightweight dynamic mechanisms that detect and adapt to the flows at run time as well as new hardware structures for efficient inter-accelerator data communication and task coordination.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.