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| Funder | National Science Foundation (US) |
|---|---|
| Recipient Organization | Silicon Assurance Llc |
| Country | United States |
| Start Date | Apr 01, 2021 |
| End Date | Sep 30, 2022 |
| Duration | 547 days |
| Number of Grantees | 2 |
| Roles | Principal Investigator; Co-Principal Investigator |
| Data Source | National Science Foundation (US) |
| Grant ID | 2036234 |
The broader impact/commercial potential of this Small Business Technology Transfer (STTR) Phase I project is to address the security challenges that currently exist in integrated circuit (IC) design and the electronic design automation (EDA) software market. It will create a platform for ‘secure-by-design' of integrated circuits using untrusted third-party intellectual property blocks.
It will provide a tool to semiconductor designers to automatically analyze security vulnerabilities and address them before fabrication. Such a capability will lead to security improvement of the fabricated chips and the systems they are integrated into, while also reducing the cost and time for secure system design through automation of vulnerability analysis and mitigation.
The proposed toolset will address a critical technology gap in the semiconductor design and EDA marketplace.
This Small Business Technology Transfer (STTR) Phase I project will develop a netlist assessment toolset which analyzes gate-level netlist of third-party integrated circuit (IC) design blocks used in modern system-on-chip (SoC) designs. The toolset converts the gate-level netlist to readable formats to support the existing security analysis tools in the electronic design automation (EDA) software market.
During gate-level security analysis, this toolset will enable the detection of vulnerability for piracy, reverse engineering, as well as malicious logic in a design. To make the toolset market ready for our customers in the EDA and semiconductor industry, the SBIR/STTR Phase I project will mainly focus on scalability testing, interface design, analysis of security benefits, and performance improvement.
Scalability testing of the toolset will be performed internally and with EDA industry customers to demonstrate the capability of the toolset in analyzing and converting the gate-level netlist of large scale SoCs.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
Silicon Assurance Llc
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