Certifiable System-on-Chip for Safety Critical Industrial Applications

Purpose and goal:

The project has developed a hardware platform with the objective to be implemented on ASIC that is extended with functions to provide time isolation between software instances. The platform has undergone an evaluation according to Common Criteria to ensure that the functions satisfactorily allow software instances to be partitioned.

Expected results and effects:

Results and experiences from the project have been used to improve Gaisler´s future standard products, an IP core is developed by Chalmers, and allows atsec to market its expertise in the area. Approach and implementation:

The project was planned with the phases Specification, Design, Implementation and verification, and Demonstrator phase. Parallel to these phases, a Security Evaluation ran where design choices and documentation for the design were reviewed and continuously improved. Establishing the initial design and extensions for interprocessor timing isolation went well.

Extensions of the NoC were more time-consuming due to technical difficulties. At this stage, the project should have prioritized documentation extensions in order not to delay the work with the security evaluation.