Exploration of Back-End-Of-Line Compatible Te-Based P-Type Transistors With 2D Material Van Der Waals Contacts for Monolithic 3D Integration

The performance enhancement of integrated circuits relying on the downscaling of transistor dimensions following Moore’s law is becoming more and more challenging as silicon is reaching its physical limit. Thus, monolithic 3D integration has been considered as a powerful method to improve system performance further.

This requires that transistors be stacked on top of each other at back-end-of-line (BEOL) compatible temperatures to avoid degradation of underlying devices.

Two-dimensional (2D) semiconductors are promising candidates for such BEOL transistors but most advancements in terms of device performance and reliable BEOL integration concern n-type devices, while p-type is still lagging behind.

Hence, better p-type BEOL transistors are highly sought after to enable complementary metal oxide semiconductor (CMOS) technology.

One of several challenges for p-type devices is contact resistance because wide band gap 2D semiconductors typically have large Schottky barriers between the metal contact and their valence band.

Tellurium (Te) and its compounds have recently been identified as promising candidates for BEOL p-type 2D transistors, which offer decent access to their valence bands, integration at BEOL-compatible temperatures, and good material prospects for device performance.

However, research on such devices is still in its infancy, and drive current, stability (passivation), and contact resistance still need improvements. Thus, in this work, we propose to advance the research in Te-based p-type devices. In particular, we will experimentally explore the potential of 2D material van der Waals contacts.

Furthermore, we will evaluate the CMOS logic circuit performance coupling with its n-type counterpart and the prospects of our devices for monolithic 3D integration through simulation.